What Happens When One Core Reaches a Synchronization Barrier Later Than the Others?
emmtrix Tech Posts
Category: Verilator Cluster
Our public four-core RISC-V simulation setup includes a barrier stress test for exploring exactly that, with one slower core and three faster cores.
The emmtrix Technologies repository provides a standalone Verilator testbench for a cluster of four CV32E40P cores. It includes shared memory and a 256 KiB scratchpad per core, with each scratchpad accessible by all four cores.
Example applications cover shared-memory access, parallel reduction, tiled matrix multiplication, and synchronization.
For engineers exploring embedded multicore software, this provides a concrete starting point. You can run the examples, inspect the implementation, or adapt the code for your own experiments without a physical target board.
The repository includes build and run instructions, a pytest-based smoke test, and optional waveform tracing to inspect simulation behavior.
Embedded software analysis, optimization, and parallelization are part of our work at emmtrix. By sharing this testbench, we provide a practical resource for engineers to explore how software runs and interacts across multiple cores.
Access the source code, setup instructions, and example applications:
The public verification testbench models a 4-core CV32E40P RISC-V cluster with shared memory, I/O, and local scratchpad memories.