Static Performance Estimation for Embedded Processors based on Compiler Intermediate Representations
October 14, 2021
We are proud to see that the master thesis of one of our former working students, Mrs. Pranjal Ranka, got featured on the website of Hector School, KIT (https://www.hectorschool.kit.edu/master-thesis-topics.php):
The end of single-core processors has come! New processors are increasingly characterized by heterogeneous multi-core processors. This is because only heterogeneous multicore processors can efficiently use the ever-increasing number of transistors to increase performance. However, multicore processors shift the problem of parallelization from hardware to software. As a result, the programmer is responsible for parallelizing the application and has to deal with parallelization issues. Therefore, we at emmtrix are researching automatic parallelization of C code for heterogeneous multicore processors. For automatic parallelization a performance estimation of the sequential input application is important. The previous performance estimation is only based on C code and therefore does not consider the influence of compiler optimizations. With this thesis, a new performance estimation is developed using LLVM compiler intermediate representation (IR).
Pranjal Ranka, Information Systems Engineering and Management, Intake 2019
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